![]() Same sequence for logsweep, but the recorded file was converted to 16-bit with CoolEdit before running the convolution with the inverse logsweep analog output connected to PC soundcard Digigram VXpocket passive I/V stage as per DDDAC project (active stage disconnected) Workflow sequence: (only 1 Parallella used in loopback) Mono only for now Attachments diagram.jpg (79.75 KiB) Viewed 35476 times Parallella DAC.jpg (235.45 KiB) Viewed 35476 times patc Posts: 83 Joined: Wed 7:18 pm The feasibility prototype to test both DAC-PCM and DAC-DSD using the same DSD1794 The SDM module has been designed by researchers from UK Unfortunately the DSD1794 digital attenuation feature is available with OS mode only so I need to add volume control which I plan to do in the analog domain and I bought a couple of different ICs (MAS6116 and CS3310) to try out Still plenty of work to do but so far so good, the first results sound promising Since the TI DSD1794 DAC supports both oversampling (OS) and non-oversampling (NOS) as per the DDDAC project, first I planned to do a listening compare between those 2 PCM modes.īut this recent article on the Xilinx blog, also kindly pointed out by Andreas, looks pretty interesting as well: Among his numerous skills, his knowledge of the Tact digital amps is awesome. Many thanks again to Christophe, the friend who helped me to decipher the digital amps serial protocol. The 8-bit uController can then adjust the DAC attenuation based on the value it decodes from the RS232 port. The volume is set with a remote control on one digital amp which broadcasts the value through RS232 to the other digital amps linked together. ![]() The DSD1794 features a user programmable (I2C) digital attenuator for volume control. the SPDIF receiver (CS8416) and 8-bit microcontroller to test I2C/RS232/clock the DAC (DSD1794) with op-amps connected directly to the FPGA while testing both I2S and I2C Parallella is mating with ole'timer 300B triode (Sophia Electric)įor initial prototyping, the DAC module is split in 2:
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